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This paper proposes a new design of a highly stable and low-power static RAM (SRAM) cell using carbon nanotube FETs (CNTFETs) that utilizes different threshold voltages for best performance. In a CNT, the threshold voltage can be adjusted by controlling the chirality vector (i.e., the diameter). In the proposed six-transistor SRAM cell design, while all CNTFETs of the same type have the same chirality, n-type and p-type transistors have different chiralities, i.e., a dual-diameter design of SRAM cell. As figures of merit, stability, power dissipation, and write time are considered when selecting the chirality for the best overall performance. A new metric, denoted as ??SPR,?? is proposed to capture these figures of merit. This metric shows that a CNTFET-based SRAM cell provides an ??SPR?? that is four times higher than for its CMOS counterpart that has the same configuration, thus attaining superior performance. Finally, the sensitivity of the CNTFET SRAM design to process variations is assessed and compared with its CMOS design counterpart. Extensive simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based SRAM cell due to variations in the diameter, supply voltage, and temperature of the CNTFETs. The CNTFET-based SRAM cell demonstrates that it tolerates the process, power supply voltage, and temperature variations significantly better than its CMOS counterpart.