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We introduce an implementation of a radix 4 dual recoding procedure for the squaring operation of an n-bit number which reduces the number of bit product terms employed in the previously known squaring methods obtained by either Booth radix-4 recoded multiplication or by radix 2 squaring. Several other squaring algorithms have been developed such as [WSM99], [YW01], and [SNC01]. Employing the dual recoded radix-4 procedure for design of a squaring circuit introduces a significant reduction in power and area. Architecturally, radix-4 dual recoded squaring uses only the 1's complement representation which allows for a simpler PPG structure as compared to the 2's complement representation required for Booth radix-4 multiplication.