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Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects

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12 Author(s)
Vempati, S.R. ; Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore ; Su, N. ; Chee Houe Khong ; Ying Ying Lim
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Continuous increase in demand for product miniaturization, high package density, high performance and integration of different functional chips has lead to the development of three dimensional packaging technologies. Face-to-face silicon (Si) dies stacking is one of the three dimensional (3D) packaging technologies to form a high density module. In this work, a chip level stacked module was demonstrated for medical application and assessed its package level reliability. The chip level stack module is achieved by stacking two thin dies of different size and thickness together using flip chip technology with micro bump interconnects. Electrical simulations are carried out to obtain RLC parameters of micro bump interconnect and complete interconnection from daughter die to substrate. Mechanical simulations are also carried out to study the stress analysis on micro bumps and CSP bumps in the package and parametric study of stacked module package to study the effect of substrate material, underfill material die thicknesses on package reliability and warpage. Test chips are designed and fabricated with daisy chain test structures to access the reliability of the stack module. Pb-free (SnAg) micro bumps of 40 mum on daughter die wafers and eutectic SnPb solder CSP bumps of 200 mum height on mother die wafers are fabricated. Mother die and daughter die bumped wafers were thinned to 300 mum and 60 mum respectively using mechanical backgrinding method. These thin dies are stacked using chip to wafer flip chip bonding and underfill process is established for the micro bump interconnects. The assembled Si die stacked modules are subjected to JEDEC package level reliability tests in terms of temperature cycle test (TC), high temperature storage test (HTS), moisture sensitivity test level 1 (MST L1) and MST L3, and un-biased high accelerated stress test (uHAST) and results are presented.

Published in:

Electronic Components and Technology Conference, 2009. ECTC 2009. 59th

Date of Conference:

26-29 May 2009