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Thermal management of 3D IC integration with TSV (through silicon via)

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2 Author(s)
Lau, J.H. ; Dept. of Mech. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong ; Yue, T.G.

Thermal performances of 3D stacked TSV (through silicon via) chips filled with copper are investigated based on heat-transfer CFD (computational fluid dynamic) analyses. Emphases are placed on the determination of (1) empirical equations for the equivalent thermal conductive of chips with various copper-filled TSV diameters, pitches, and aspect ratios, (2) the junction temperature and thermal resistance of 3D stacking of up to 8 TSV chips, and (3) the effect of thickness of the TSV chip on its hot spot temperature. Useful design charts and guidelines are provided for engineering practice convenient.

Published in:

Electronic Components and Technology Conference, 2009. ECTC 2009. 59th

Date of Conference:

26-29 May 2009