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Because of Moore's (scaling/integration) law, the Cu/low-k silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips anymore. To address these needs, Si interposer with TSV has emerged as a good solution to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 times 21 mm Cu/low-k test chip on FCBGA package. The Cu/low-k chip is a 65 nm, 9-metal layer chip with 150 mum SnAg bump pitch of total 11,000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 times 25 times 0.3 mm with CuNiAu as UBM on the top side, and SnAgCu bumps on the underside. The conventional BT substrate size is 45 times 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free micro solder bumps and underfill have been set up. The FCBGA samples have been subjected to moisture sensitivity test and thermal cycling (TC) reliability assessments.