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Engineering nano interfacial layers for low contact resistance in chip to package interconnects

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8 Author(s)
Xu, J.S. ; Freescale Semicond. Inc., Tempe, AZ ; Ramanathan, L. ; Cruau, D. ; Chen, J.
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This paper presents a study on the contact resistance of interconnects between chip and package of embedded chip technology. Multi-layered aluminum/titanium tungsten/copper interconnects (Al/TiW/Cu) were used as the model system. Design of experiment was carried out to characterize the effect of under bump metallurgy deposition steps, including the degas and radio frequency (RF) plasma etch steps, on contact resistance. A minimum level of degassing is needed, but the resistance was significantly affected by the amount of RF etch. Extensive failure analysis was done using focus ion beam (FIB), Auger electron spectroscopy (AES), scanning electron microscope (SEM), high resolution transmission electron microscope (HRTEM), and secondary ion mass spectroscopy (SIMS) to correlate the resistance to the quality of the bond pad surface and its interface with overlying TiW/Cu under bump metallurgy layers. With a carefully engineered solution, the contact resistance of aluminum/titanium tungsten/copper interconnects between chip and package was reduced almost 3 orders of magnitude to 10 milliohm range. FIB, SEM, AES, HRTEM, and SIMS were used to characterize the nano interfacial layers of both high contact resistance and low contact resistance samples. HRTEM showed the presence of a distinct interfacial layer between TiW and Al interface for both high and low resistance samples, which has not been reported before. The thickness and composition were characterized using SIMS and HRTEM. The macroscopic resistance characteristics were correlated to the state of the interface as established by SIMS and HRTEM.

Published in:

Electronic Components and Technology Conference, 2009. ECTC 2009. 59th

Date of Conference:

26-29 May 2009

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