Cart (Loading....) | Create Account
Close category search window

Engineering nano interfacial layers for low contact resistance in chip to package interconnects

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Xu, J.S. ; Freescale Semicond. Inc., Tempe, AZ ; Ramanathan, L. ; Cruau, D. ; Chen, J.
more authors

This paper presents a study on the contact resistance of interconnects between chip and package of embedded chip technology. Multi-layered aluminum/titanium tungsten/copper interconnects (Al/TiW/Cu) were used as the model system. Design of experiment was carried out to characterize the effect of under bump metallurgy deposition steps, including the degas and radio frequency (RF) plasma etch steps, on contact resistance. A minimum level of degassing is needed, but the resistance was significantly affected by the amount of RF etch. Extensive failure analysis was done using focus ion beam (FIB), Auger electron spectroscopy (AES), scanning electron microscope (SEM), high resolution transmission electron microscope (HRTEM), and secondary ion mass spectroscopy (SIMS) to correlate the resistance to the quality of the bond pad surface and its interface with overlying TiW/Cu under bump metallurgy layers. With a carefully engineered solution, the contact resistance of aluminum/titanium tungsten/copper interconnects between chip and package was reduced almost 3 orders of magnitude to 10 milliohm range. FIB, SEM, AES, HRTEM, and SIMS were used to characterize the nano interfacial layers of both high contact resistance and low contact resistance samples. HRTEM showed the presence of a distinct interfacial layer between TiW and Al interface for both high and low resistance samples, which has not been reported before. The thickness and composition were characterized using SIMS and HRTEM. The macroscopic resistance characteristics were correlated to the state of the interface as established by SIMS and HRTEM.

Published in:

Electronic Components and Technology Conference, 2009. ECTC 2009. 59th

Date of Conference:

26-29 May 2009

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.