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With the rapid advance of enabling technologies, the era of 3D ICs is near. Yet, there are several practical problems to be solved for 3D ICs. Especially, heat removal and power delivery have become two major reliability concerns in 3D stacked IC technology. Recently, liquid cooling based on micro-fluidic channels is proposed as a viable solution to dramatically reduce the temperature of 3D ICs. In addition, a highly complex power distribution network is required to deliver currents to all parts of the 3D IC stack while suppressing power noise to an acceptable level. These technologies pose major challenges to signal routing. With a given amount of silicon area, signal, power, and thermal interconnects compete against one another for routing space. This paper presents an optimization study on signal, power, and thermal networks in 3D ICs. We demonstrate how to optimize various design parameters by adopting design of experiments and response surface method.