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Development of silicon module with TSVs and global wiring (L/S=0.8/0.8µm)

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6 Author(s)
Masahiro Sunohara ; Technology and Application Development Department, Research and Development Division, Shinko Electric Industries Co., LTD., Kita Owaribe 36 Nagano-shi, Nagano, 381-0014 Japan ; Akinori Shiraishi ; Yuichi Taguchi ; Kei Murayama
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In recent years, in order to achieve high density and high transmission speed between chips, various kinds of silicon modules have been developed. Our purpose is the development of silicon module in which several chips are mounted on the silicon substrate with Cu-Through Silicon Vias (Cu-TSVs) and fine multilayer Cu wirings such as global layer of devices. Since silicon substrate has a quite flat and smooth surface, fine wirings such as the global layer of devices can be formed. Furthermore, silicon interposer can be applied to a substrate, which show high reliability of micro bump interconnection for the reason of its same Coefficient of Thermal Expansion (CTE) with silicon devices. In this paper, key technologies required for the silicon interposer, that is, fabrication of submicron wiring on the silicon interposer, 1st level interconnection by Transient Liquid Phase (TLP) diffusion bonding, stress reduction at 2nd level interconnection using "Trenched Air Gap (TAG)-TSV" are reported. Finally signal integrity and stability of power/ground delivery for logic devices are also described.

Published in:

2009 59th Electronic Components and Technology Conference

Date of Conference:

26-29 May 2009