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A 1V, 2.4 GHz low power CMOS receiver front end for wireless micro sensor nodes

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2 Author(s)
T. Sasilatha ; Anna University, Chennai - 25, India ; J. Raja

This paper focuses on the modified design, measurements and implementations of receiver front end targeted for wireless sensor network applications. Key issues in wireless sensor network receivers are discussed and the existing circuit level implementations of low noise amplifiers are compared. Emphasis was placed on observing device reliability constraints at low power to maximize the life time of the wireless sensor nodes. The proposed architecture can operate at 2.4 GHz and dissipates a power of 22.6 muw from a 1 V supply. A noise figure of 3.9 dB at 20 db gain and IIP3 of -3.1 dBm was obtained. The noise performance at input, output and the frequency response is presented.

Published in:

Communications, Signals and Coding, 2008. MIC-CSC '08. Proceedings of the Mosharaka International Conference on

Date of Conference:

17-19 Oct. 2008