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The design of a latency constrained, power optimized NoC for a 4G SoC

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4 Author(s)
Beraha, R. ; Qualcomm Corp. Res. & Dev., San Diego, CA ; Walter, I. ; Cidon, I. ; Kolodny, A.

Network on-Chip (NoC) is being adopted by chip architects as a means to improve design productivity. As the number of modules connected to a bus increase, its physical implementation becomes very complex, and achieving the desired throughput and latency requires time consuming custom modifications. Conversely, NoCs are designed separately from the functional units of the system to handle all foreseen inter-module communication needs. Their inherent scalable architecture facilitates the integration of the system and shortens the time-to-market of complex products. In this work, we discuss and evaluate the design process of a NoC for a state-of-the-art system on-chip (SoC). More specifically, we describe our experience in designing a cost optimized NoC interconnect for a high-performance, power constrained 4G wireless modem. We focus on the power and performance aspects of various module mapping schemes, looking for a tradeoff that is characterized by a minimal power consumption that still meets the timing requirements of all targeted applications. Using a simulated annealing based mapping process, we place the system's modules on a grid, minimizing the dynamic energy consumed by the transmission of packets over the NoC.

Published in:

Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on

Date of Conference:

10-13 May 2009