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Optimal  \Sigma \Delta Modulator Architectures for Fractional-  {N} Frequency Synthesis

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5 Author(s)
Sleiman, S.B. ; Analog VLSI Lab., Ohio State Univ., Columbus, OH, USA ; Atallah, J.G. ; Rodriguez, S. ; Rusu, A.
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This paper presents a comparative study of ΣΔ modulators for use in fractional-N phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 2 )