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Techniques to Prioritize Paths for Diagnosis

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2 Author(s)
Adapa, R. ; Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA ; Tragoudas, S.

Existing techniques for path delay fault (PDF) diagnosis prune fault-free candidates using nonfailing patterns but fail to reduce the size of suspect set significantly. This paper presents two alternative techniques that can be applied in a postprocessing manner to further reduce the suspect set by prioritizing paths using only the failing patterns. Experimental results on the ISCAS benchmarks demonstrate that they are time and memory efficient.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 4 )