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This paper describes a tool called rapport which prepares rearchitected designs for sequential equivalence checking. This tool is applicable when an existing "golden" design is optimized for higher performance. Without such a tool, the optimizations would need to remain within a single module boundary, since equivalence checking tools require a one-to-one mapping between ports when proving two designs are equivalent. The tool is also able to handle arbitrary encodings of reference signals to produce design signals and retiming of signals.
Date of Conference: 8-10 Dec. 2008