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In this paper, a design and implementation of an efficient, low power log-based 2D convolution unit (convolver) for video processing applications is proposed. The design of the proposed convolver utilizes approximation method with error correction technique to transform data to logarithmic domain for reduced power consumption. A novel design and implementation of a modular approach for leading bit detection module that is used to compute the binary logarithm is presented. A partitioning and gating technique is also presented to reduce the switching activities based on detection of insignificant data bits. It is observed that the proposed logarithmic-domain multiplier reduces power consumption in two common image filtering operations by more than 50% compared to conventional linear-domain 2D convolvers.
Date of Conference: 27-29 April 2009