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Noise analysis of low noise, high count rate, PIN diode X-ray detectors

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2 Author(s)
Zhou, C.Z. ; X-ray Instrum. Associates, Mountain View, CA, USA ; Warburton, W.K.

A noise analysis for a planned PIN diode X-ray detector array using CMOS technology explores the affect of allowed device dimensions on attainable energy resolution using a methodology which allows low frequency, process dependent 1/f and 1/f2 terms to be explicitly evaluated for arbitrary noise filters. We find that enhancement mode MOSFETs are too noisy for this application while, for peaking times τp<1 μs and carefully processed buried channel depletion mode MOSFETs, both 1/f and 1/f2 terms are negligible and the classical approaches to minimizing noise (reducing gate lengths and minimizing capacitances) remain valid. A concrete example demonstrates expected performance: namely a ΔE of 53 eV FWHM for a 180 ns τp at 300 K using a 0.1 pF detector coupled to a 0.5 μm gate length input transistor

Published in:

Nuclear Science, IEEE Transactions on  (Volume:43 ,  Issue: 3 )

Date of Publication:

Jun 1996

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