By Topic

Processor Allocation Problem for NoC-Based Chip Multiprocessors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Zydek, D. ; Dept. of Electr. & Comput. Eng., Univ. of Nevada, Las Vegas, NV ; Selvaraj, H.

Chip multiprocessors (CMPs) have become the primary approach to build high-performance microprocessors. Such systems require fast and efficient communication that can only be realized using network on chip (NoC), particularly for large systems. Allocation and management of on-chip processors are also important factors to achieve high efficiency. Designing processor allocator, job scheduler and NoC are major issues for future CMPs. In this paper we analyze architectures of NoC for CMPs. Such NoC parameters as topology, flow control and routing are studied and proposed for CMPs implementation. Modern processor allocation algorithms together with scheduling techniques are reviewed and suggested. Hardware structure of NoC-based CMPs is introduced for the recommended solutions. We propose hardware implementation of processor allocator and job scheduler, and place them together with on-chip processors on the same die.

Published in:

Information Technology: New Generations, 2009. ITNG '09. Sixth International Conference on

Date of Conference:

27-29 April 2009