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A DPA-Resistant Digit-Parallel Modular Multiplier over GF (2m)

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2 Author(s)
Jianping Quan ; Inst. of Microelectron., Tsinghua Univ., Beijing ; Guoqiang Bai

Researches on DPA-resistant ECC implementation are concentrated in algorithm level. All these countermeasures need a big random number and extra memory overhead which are rare resources in hardware. On the other hand, universal countermeasures in logic level have a big area overhead and face many popular DPA attacks. To avoid these disadvantages, we attempt to solve it in architecture level. This paper presents a DPA-resistant digit-Parallel modular multiplier over GF (2m) which can be used to conceive a secure ECC implementation. It uses 1-bit random number and brings about 20% overhead in speed, 50% overhead in area and 75% overhead in power. Simulations based on back-annotated netlists show that our method can prevent popular DPA attacks successfully.

Published in:

Information Technology: New Generations, 2009. ITNG '09. Sixth International Conference on

Date of Conference:

27-29 April 2009

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