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Low-power, high-gain and low-noise CMOS distributed amplifier for UWB systems

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2 Author(s)
Chang, J.-F. ; Dept. of Electr. Eng., Nat. Chi Nan Univ., Puli ; Lin, Y.-S.

A 3-10-GHz CMOS distributed amplifier (DA) with flat and low noise figure (NF) and flat and high power gain (S21) is demonstrated. A flat and low NF was achieved by adopting an RL terminating network for the gate transmission line, and a slightly under-damped Q-factor for the second-order NF frequency response. Besides, an flat and high S 21 was achieved by using the proposed cascade gain cell, which constitutes a cascode-stage with a low-Q RLC load and an inductive-peaking common-source stage. In the high-gain mode, the DA consumed 37.8 mW and achieved a flat and high S 21 of 20.47plusmn0.72 dB with an average NF of 3.29plusmndB over the 3plusmn10plusmnGHz band of interest, one of the best reported NF performances for a CMOS UWB DA or low-noise amplifier. In the low-gain mode, the DA achieved S 21 of 11.03plusmn0.98plusmndB and an average NF of 4.25plusmndB with a power dissipation (PD) of 6.86 mW, the lowest PD ever reported for a CMOS UWB DA or LNA with an average S 21 of greater than 10 dB.

Published in:

Electronics Letters  (Volume:45 ,  Issue: 12 )

Date of Publication:

June 4 2009

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