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FPGA-driven pseudorandom number generators aimed at accelerating Monte Carlo methods

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2 Author(s)
Bachir, T.O. ; Dept. of Electr. Eng., Ecole Polytech. de Montreal, Montreal, QC, Canada ; Brault, J.

Hardware acceleration in high performance computing (HPC) context is of growing interest, particularly in the field of Monte Carlo methods where the resort to field programmable gate array (FPGA) technology has been proven as an effective media, capable of enhancing by several orders the speed execution of stochastic processes. The spread-use of reconfigurable hardware for stochastic simulation gathered a significant effort towards effective implementations of hardware pseudorandom numbers generators (PRNGs) - these generators needed to exhibit a statistically proven random behaviour and to be characterized by a very long period. In this paper we present the state of the art of hardware pseudorandom number generation in the context of Monte Carlo acceleration. We highlight the emerging trends over the most recent publications and suggest some insights on the forthcoming works. Furthermore, we provide a complete hardware description of a new Gaussian variate generator (GVG) and an exponential variate generator (EVG) based on a decision-tree technique of ours, herein presented as well. The prototypes implemented on a Xilinx Virtex II Pro XC2VP100 FPGA occupy from 150 to 417 slices and reach 280 MHz, while exhibiting good statistical behaviours with high p-values on the x2 test and offering a unitary Knuth ratio.

Published in:

Computer Systems and Applications, 2009. AICCSA 2009. IEEE/ACS International Conference on

Date of Conference:

10-13 May 2009