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System in Package (SiP) With Reduced Parasitic Inductance for Future Voltage Regulator

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6 Author(s)
Hashimoto, T. ; Hitachi Res. Lab., Hitachi, Ltd., Hitachi ; Shiraishi, M. ; Akiyama, N. ; Kawashima, T.
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A system in package (SiP) that integrates high-side and low-side MOSFETs and their driver IC has been developed for voltage regulators. Compared with the conventional discrete package, the SiP offers 25% lower power loss because it has low parasitic inductances. The peak drain voltage of the low-side MOSFET during turn- on of the high-side MOSFET is 45% lower than that of the discrete package, and this improves switching noise characteristics and lowers MOSFET conduction losses because it decreases the MOSFET breakdown voltage. A mixed-mode simulation was performed that indicated the common-source parasitic inductance should be reduced in order to attain low switching loss. To reduce this common-source parasitic inductance, the source pad of the high-side MOSFET is bonded directly to the driver IC with a wire.

Published in:

Power Electronics, IEEE Transactions on  (Volume:24 ,  Issue: 6 )

Date of Publication:

June 2009

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