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Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic

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4 Author(s)
Tsung-Te Liu ; Berkeley Wireless Res. Center, Univ. of California, Berkeley, CA, USA ; Alarcon, L.P. ; Pierson, M.D. ; Rabaey, J.M.

This paper presents the design and implementation of a low-energy asynchronous logic topology using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low-leakage pass transistor networks at low supply voltages. The introduction of asynchronous operation in SAPTL further improves energy-delay performance without a significant increase in hardware complexity. We show two different self-timed approaches: 1) the bundled data and 2) the dual-rail handshaking protocol. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation and measurement results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled data self-timed approaches in 90-nm CMOS.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:17 ,  Issue: 7 )