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Configuration Locking and Schedulability Estimation for Reduced Reconfiguration Overheads of Reconfigurable Systems

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2 Author(s)
Kalra, R. ; Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ, USA ; Lysecky, R.

Dynamically reconfigurable field-programmable gate arrays (FPGAs) hold the promise of providing a virtual hardware resource in which hardware circuits can be dynamically scheduled onto the available FPGA resources. However, reconfiguring an FPGA can incur significant performance and energy overheads. This paper analyzes the relationship between several hardware task scheduling algorithms and their impact on the number of reconfigurations required to execute a set of hardware tasks. In addition, three new hardware scheduling algorithms, specifically designed to reduce the number of required reconfigurations, are presented and analyzed. By selectively locking configurations within the reconfigurable tiles of an FPGA, significant reductions in the number of required reconfiguration can be achieved.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 4 )

Date of Publication:

April 2010

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