Referenced Items are not available for this document.
All-digital phase locked loops (DPLLs) have many advantages over analog loops. However, due to digital device limitations and costs, superwide PLLs with front-end bandwidths as high as one gigahertz are commonly implemented using analog parts. This article presents a new architecture that allows an all-digital implementation of superwide PLLs. The problem of operating digital components at high speed is avoided here (without reducing the front-end bandwidths) by inserting a multirate digital filter bank in front of the DPLL. The new design is shown to have steady-state and transient performance that is identical to a conventional DPLL
Published in:
Communications, IEEE Transactions on
(Volume:44
,
Issue:
6
)
Date of Publication: Jun 1996
- Page(s):
- 663 - 667
- ISSN :
- 0090-6778
- INSPEC Accession Number:
- 5305903
- Digital Object Identifier :
- 10.1109/26.506382
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Jun 1996
- Sponsored by :
- IEEE Communications Society
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