By Topic

The Influence of TiN Thickness and \hbox {SiO}_{2} Formation Method on the Structural and Electrical Properties of \hbox {TiN}/ \hbox {HfO}_{2}/\hbox {SiO}_{2} Gate Stacks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)

In this brief, we report on how controllable process parameters such as metal-gate physical thickness and interfacial-layer-formation method affect the electrical and structural properties of TiN/HfO2/SiO2 gate stacks. We found evidence that Hf is diffusing into chemically formed SiO2 interfacial layers during device processing. The latter is not seen when SiO2 is formed thermally. We show that the interfacial layer is thinner when the physical thickness of TiN is reduced from 7 to 3 nm, resulting in electrically thinner gate stacks by 2 Aring. An electrical thickness in inversion as low as 11.4 Aring with gate-leakage-current density equal to 3.5 A/cm2 at 1 V was obtained for spike-annealed thin TiN/HfO2 stacks on chemically grown interfaces. Hf-rich chemical interfacial oxides do not degrade device performance. A small reduction in transconductance is only seen for physically thinner interfacial layers.

Published in:

IEEE Transactions on Electron Devices  (Volume:56 ,  Issue: 7 )