Skip to Main Content
A capacitorless 1T-DRAM is fabricated on a fully depleted poly-Si thin-film transistor (TFT) template. A heavily doped back gate with a thin back-gate dielectric is employed to facilitate the formation of a deep potential well that retains excess holes. An asymmetric double gate (n+ front gate and p+ back gate) shows a wider sensing current window than a symmetric double gate (n+ front gate and n+ back gate). This is attributed to the inherent flatband voltage between the p+ back gate and the channel inducing a deeper potential well, which allows capacitorless 1T-DRAM operation at a low back-gate voltage. The TFT capacitorless 1T-DRAM can be applied for future stackable memory for the ultrahigh density era.