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Redundancy design for a fault tolerant systolic array

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2 Author(s)
Wang, J.-J. ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Jen, C.-W.

A systematic design methodology for redundant systolic arrays is proposed. Redundancies consisting of space-shift, time-shift and space-time-shift schemes are applied successfully to detect or mask permanent faults, transient faults or both. Various redundancy designs for different utilisation efficiencies of processor elements can be obtained at the design stage by a dependent graph and its associated algebraic transformation. A customised optimal redundant systolic array design can be achieved for various performance requirements, including throughput rate, latency, average computation time, hardware cost and capabilities of fault detection and fault masking.

Published in:

Computers and Digital Techniques, IEE Proceedings E  (Volume:137 ,  Issue: 3 )