By Topic

Development and synthesis method for pass-transistor logic family for high-speed and low power CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Oklobdzija, V.G. ; Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA ; Soderstrand, M. ; Duchene, B.

This paper presents a new pass-transistor logic termed DVL which contains fewer transistors and has better performance than other CMOS logic families. A method for synthesis of DVL is also developed and demonstrated. This new logic has advantages over CMOS and is characterized by excellent speed and low power

Published in:

Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on  (Volume:1 )

Date of Conference:

13-16 Aug 1995