By Topic

Worst case analysis of low-voltage analog MOS integrated circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Hing-Yan To ; Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA ; Michael, C. ; Ismail, M.

A methodology for worst case analysis of low voltage analog MOS integrated circuits is presented. It relates parameter to current mismatch in a transistor pair analytically and the current mismatch is regarded as a random variable. It is shown that the algorithm is efficient and is readily extended to the circuit level. The effect of the active area of critical transistor pairs is also investigated. The methodology is used to study the DC offset in low voltage CMOS op amps

Published in:

Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on  (Volume:1 )

Date of Conference:

13-16 Aug 1995