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A Petri net approach to the design of processor array architectures

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3 Author(s)
K. E. Karagianni ; Dept. of Electr. Eng., Patras Univ., Greece ; D. J. Soudris ; T. Stouraitis

In this paper, a methodology for deriving processor array architectures that meet desired specifications for nested-loop algorithms is introduced. The methodology is based upon the construction of a Petri net model for the dependencies of the algorithm, the development of a forest of reachability trees for this model and the creation of an execution graph. Different executions of the algorithm are found on the reachability tree forest through a proposed function, leading to different architectures that implement the algorithm. The main advantage of this method is that it may easily lead to non-homogeneous architectures

Published in:

Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on  (Volume:1 )

Date of Conference:

13-16 Aug 1995