By Topic

A Petri net approach to the design of processor array architectures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Karagianni, K.E. ; Dept. of Electr. Eng., Patras Univ., Greece ; Soudris, D.J. ; Stouraitis, T.

In this paper, a methodology for deriving processor array architectures that meet desired specifications for nested-loop algorithms is introduced. The methodology is based upon the construction of a Petri net model for the dependencies of the algorithm, the development of a forest of reachability trees for this model and the creation of an execution graph. Different executions of the algorithm are found on the reachability tree forest through a proposed function, leading to different architectures that implement the algorithm. The main advantage of this method is that it may easily lead to non-homogeneous architectures

Published in:

Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on  (Volume:1 )

Date of Conference:

13-16 Aug 1995