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A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

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3 Author(s)
Santos, D.M. ; Aveiro Univ., Portugal ; Dow, S.F. ; Levi, M.E.

Many high energy physics and nuclear science applications require sub-nanosecond time resolution measurements over marry thousands of detector channels. Phase-locked loops have been employed in the past to obtain accurate time references for these measurements. An alternative solution, based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Muller C element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multi-channel, time to digital converter (TDC). Complex clock generation can be achieved by taking symmetric taps off the delay elements. The two circuits, DLL and TDC, were implemented in a CMOS 1.2 μm and 0.8 μm technology, respectively. Test results show a timing jitter of less than 35 ps for the DLL circuit and better than 135 ps resolution for the TDC circuit

Published in:

Nuclear Science Symposium and Medical Imaging Conference Record, 1995., 1995 IEEE  (Volume:1 )

Date of Conference:

21-28 Oct 1995