Cart (Loading....) | Create Account
Close category search window
 

Modeling and simulation of broken connections in CMOS IC's

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Favalli, M. ; Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy ; Dalpasso, M. ; Olivo, P.

This paper presents a fault model, called node-break fault model, to effectively account for broken connections inside CMOS circuits. The proposed model is very general since it allows to generate test vectors for broken connections that cannot be detected by means of test sequences for stuck-open faults. In addition, the detection of a broken connection in a node ensures the detection of all stuck-open faults of the transistors connected to that node, thus superseding the stuck-open fault model. The model can be used to derive tests and to perform fault simulations independent of the actual layout of the circuit. Conditions for the detection of broken connections are derived from electrical considerations (aimed at verifying the presence of electrical continuity between the terminals of transistors connected to a node) while the minimum number of input vectors to test for broken connections in a node is determined by graph theory. Fault simulations performed on benchmark circuits using test sequences oriented to the detection of stuck-open faults show their inadequacy in detecting node-break faults, thus claiming for considering such a fault model in the test pattern generation

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:15 ,  Issue: 7 )

Date of Publication:

Jul 1996

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.