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Modeling and simulation of broken connections in CMOS IC's

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3 Author(s)
M. Favalli ; Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy ; M. Dalpasso ; P. Olivo

This paper presents a fault model, called node-break fault model, to effectively account for broken connections inside CMOS circuits. The proposed model is very general since it allows to generate test vectors for broken connections that cannot be detected by means of test sequences for stuck-open faults. In addition, the detection of a broken connection in a node ensures the detection of all stuck-open faults of the transistors connected to that node, thus superseding the stuck-open fault model. The model can be used to derive tests and to perform fault simulations independent of the actual layout of the circuit. Conditions for the detection of broken connections are derived from electrical considerations (aimed at verifying the presence of electrical continuity between the terminals of transistors connected to a node) while the minimum number of input vectors to test for broken connections in a node is determined by graph theory. Fault simulations performed on benchmark circuits using test sequences oriented to the detection of stuck-open faults show their inadequacy in detecting node-break faults, thus claiming for considering such a fault model in the test pattern generation

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:15 ,  Issue: 7 )