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Valid clock frequencies and their computation in wavepipelined circuits

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3 Author(s)
Lam, W.K.C. ; Hewlett-Packard Co., Palo Alto, CA, USA ; Brayton, R.K. ; Sangiovanni-Vincentelli, A.L.

It is known that wavepipelined circuits offer high performance, because their maximum clock frequencies are limited only by the path delay differences of the circuits, as opposed to the longest path delays. For proper operation, precision in clock frequency is essential. Using a new representation, Timed Boolean Functions, we derive analytical expressions for valid clocking intervals in terms of topological, 2-vector, and single vector delays, both the longest and the shortest. These intervals take into account both circuit functionality and timing characteristics, thus eliminating the pessimism caused by long and short false paths, and include effects of circuit parameters such as delay variations, clock skews, and setup and hold times of flip flops. In addition, we show that these intervals subsume Cotten's lower bound on valid clock period. Further, we study the problem of computing all enact valid clocking intervals and its computational complexity by demonstrating discontinuity and nonmonotonicity of the harmonic number H(τ) (the number of valid simultaneous data waves allowed) as a function of the clock period τ. Finally, we propose algorithms to compute the exact valid intervals for a given set of harmonic numbers and demonstrate performance enhancement of balanced circuits from ISCAS benchmarks with gate delay variations

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:15 ,  Issue: 7 )