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Permissible functions for multioutput components in combinational logic optimization

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3 Author(s)
Watanabe, Y. ; Digital Equipment Corp., Hudson, MA, USA ; Guerra, L.M. ; Brayton, R.K.

This paper is concerned with logic optimization of multilevel combinational logic circuits. In the light of theoretical work of the past years, where a circuit is modeled by a Boolean network in which each node implements a single-output Boolean function, we address how a concurrent optimization over multiple nodes or components can lead to further optimization compared to conventional minimization techniques. In particular, we provide a procedure for computing maximally compatible sets of permissible relations for multiple nodes. This is a generalization of the classical notion of a compatible set of permissible functions for a single node, where no method is known for correctly computing such a maximal set. We provide a method for computing the set correctly for the general case. Based on this, we develop and implement a procedure for optimizing multiple nodes concurrently. The proposed procedure has been implemented, and we present experimental results

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:15 ,  Issue: 7 )

Date of Publication:

Jul 1996

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