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Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

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2 Author(s)
Schroder, D.K. ; Department of Electrical Engineering and Center for Low Power Electronics, Arizona State University, Tempe, Arizona 85287-5706 ; Babcock, J.A.

Your organization might have access to this article on the publisher's site. To check, click on this link:http://dx.doi.org/+10.1063/1.1567461 

We present an overview of negative bias temperature instability (NBTI) commonly observed in p-channel metal–oxide–semiconductor field-effect transistors when stressed with negative gate voltages at elevated temperatures. We discuss the results of such stress on device and circuit performance and review interface traps and oxide charges, their origin, present understanding, and changes due to NBTI. Next we discuss the effects of varying parameters (hydrogen, deuterium, nitrogen, nitride, water, fluorine, boron, gate material, holes, temperature, electric field, and gate length) on NBTI. We conclude with the present understanding of NBTI and its minimization. © 2003 American Institute of Physics.

Published in:

Journal of Applied Physics  (Volume:94 ,  Issue: 1 )

Date of Publication:

Jul 2003

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