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An analytical scheme to combine the channel component and the edge component of direct tunneling current through ultrathin gate oxides in n-channel metal–oxide–semiconductor field-effect transistors has been developed. The results obtained have been calibrated against the published experimental and numerical simulation data. The inherent simplicity of the proposed analytical model makes it suitable for implementing in circuit simulators. The proposed model is capable of predicting the tunneling current under positive as well as negative gate bias. The impact of gate-source/drain extension overlap length (edge) on total gate leakage is clearly quantified. It is demonstrated that the overlap length should be scaled to decrease the leakage power consumption and also to extend the scalability of gate oxide to lower values. © 2003 American Institute of Physics.