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A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme

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3 Author(s)
Ying-Zu Lin ; Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan ; Cheng-Wu Lin ; Soon-Jyh Chang

In high-speed Flash analog-to-digital converters (ADCs), preamplifiers are often placed in front of a comparator to reduce metastability errors and enhance comparison speed. The accuracy of a Flash ADC is mainly limited by the random offsets of preamplifiers and comparators. This paper presents a 5-b Flash ADC with a digital random offset calibration scheme. For calibration, programmable resistive devices are used as the loading devices of the second-stage preamplifiers. By adjusting the calibration resistors, the input-referred offset voltage of each comparator is reduced to be less than 1/2 LSB. Fabricated in a 0.13-??m CMOS process, experimental results show that the ADC consumes 120 mW from a 1.2-V supply and occupies a 0.18- mm2 active area. After calibration, the peak differential non-linearity (DNL) and integral non-linearity (INL) are 0.24 and 0.39 LSB, respectively. At 3.2-GS/s operation, the effective number of bits is 4.54 b, and the effective resolution bandwidth is 600 MHz. This ADC achieves figures of merit of 3.07 and 4.30 pJ/conversion-step at 2 and 3.2 GS/s, respectively.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 3 )