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Modeling the trap generation and relaxation effects in thin oxides under unipolar and bipolar high-field impulse stressing using stress-induced leakage current

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2 Author(s)
Chim, W.K. ; Centre for Integrated Circuit Failure Analysis and Reliability, Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117576 ; Tan, Y.N.

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Stress-induced leakage current, or SILC, decreases when the time between pulses (Tbp) of a periodic ac-pulse stress wave form is increased. The SILC reduction with increasing Tbp becomes less significant when the stress voltage or the pulse duration increases. Both the SILC and positive trapped charges, generated as a result of the electrical stress, decrease with increasing Tbp. The SILC reduction with increasing Tbp was found to be a result of hole detrapping. As the SILC reduction with increasing Tbp is on the order of nanoseconds time scale, it suggests that short transit-time holes are responsible for the SILC in our work. A proposed model, describing the trap generation and relaxation processes in thin oxides during transient high-field stress using unipolar and bipolar pulse wave forms, is presented in this article. Additionally, the model was extended to calculate the amount of traps generated during write/erase endurance stress of a floating-gate tunnel oxide electrically erasable and programmable read-only memory. The measured and calculated (from the proposed model) trap concentrations were shown to be in good agreement. © 2002 American Institute of Physics.

Published in:

Journal of Applied Physics  (Volume:92 ,  Issue: 11 )