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Three-Dimensional FinFET Source/Drain and Contact Design Optimization Study

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2 Author(s)
Reinaldo A. Vega ; Dept. of Electr. Eng. & Comput. Sci., Univ. of California at Berkeley, Berkeley, CA ; Tsu-Jae King Liu

The optimization of dopant-segregated Schottky (DSS) and raised source/drain (RSD) FinFETs is investigated through a 2-D and 3-D TCAD study. ldquoSilicide gatingrdquo due to fringing fields extending from a flared silicide contact degrades DSS and RSD FinFET performances. Thus, for a multifin DSS device, the individual source/drain fins should have minimal silicide flaring and be strapped with a metal bar. For large fin pitches (FPs), this results in lower intrinsic delay and much lower delay dependence on FP than optimized RSD FinFETs, which have source/drain fins strapped using lateral epitaxial growth and accessed with vias. However, RSD FinFETs achieve lower delay for small FP and fin heights (H fin) due to low via-to-gate fringing capacitance. Thus, a new structure is proposed, called the recessed strap DSS FinFET, which combines the merits of optimized DSS and RSD FinFETs in a way that provides equivalent or improved performance over all ranges of FP and H fin.

Published in:

IEEE Transactions on Electron Devices  (Volume:56 ,  Issue: 7 )