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Ultra-low latency reconfigurable Photonic Network on Chip architecture based on application pattern

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4 Author(s)
Yu Gao ; State Key Lab. of Adv. Commun. Syst. & Networks, Shanghai Jiao Tong Univ., Shanghai ; Yaohui Jin ; Chang, Zhijuan ; Weisheng Hu

This paper presents a reconfigurable Photonic Network on Chip architecture and evaluates its ultra-low latency potential. The latency performance simulation shows a 50% decrease compared to static photonic network on chip.

Published in:

Optical Fiber Communication - incudes post deadline papers, 2009. OFC 2009. Conference on

Date of Conference:

22-26 March 2009