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Design of a low-power 32 K CMOS programmable delay-line memory

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6 Author(s)
Dejhan, K. ; Ecole Nat. Superieure des Telecommun., Paris, France ; Demassieux, N. ; Colavin, O. ; Galisson, A.
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A design of a programmable digital delay based on shift registers in 1.2-μm CMOS technology is presented. The main features of this design are 20-MHz operating frequency and 200-mW power dissipation for four 1025-pixel×8-b delay lines. An integrable circuit technique for decreasing the power dissipation of the shift register is also suggested

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Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 1 )