Design of a low-power 32 K CMOS programmable delay-line memory

A design of a programmable digital delay based on shift registers in 1.2- mu m CMOS technology is presented. The main features of this design are 20-MHz operating frequency and 200-mW power dissipation for four 1025-pixel*8-b delay lines. An integrable circuit technique for decreasing the power dissipation of the shift register is also suggested.<
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