By Topic

Efficient hardware optimisation algorithm for fixed point digital signal processing ASIC design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

The authors present a novel algorithm for area minimisation in digital signal processing ASIC design. After determining the optimised fixed point representation for each signal, the proposed algorithm divides abstract operations in design description into partitions so that operations in the same partition can share a hardware module. Experimental results show the efficacy of the proposed algorithm by generating the DSP hardwares requiring smaller area under given performance constraints

Published in:

Electronics Letters  (Volume:32 ,  Issue: 11 )