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A low-power wide-band amplifier using a new parasitic capacitance compensation technique

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2 Author(s)
Wakimoto, Tsutomu ; NTT, Kanagawa, Japan ; Akazawa, Yukio

A 3-mW 800-MHz amplifier with a voltage gain of 10 dB is discussed. The parasitic junction capacitance of a transistor is the major factor limiting the bandwidth particularly for low-power amplifiers. In addition to the pole at the input node, the pole at the output node may become dominant in low-power amplifiers, which use high-speed bipolar transistors. A parasitic capacitance compensation technique to expand the bandwidth in this type of amplifier is discussed. This technique compensates for both capacitances at the input and output nodes and enhances the bandwidth and the gain-bandwidth product. The measured data demonstrate that this technique expands the bandwidth to about twice that of a conventional differential amplifier. In addition, circuit simulation predicts that this technique expands the bandwidth by about 40% over a conventional peaking technique. A stable frequency response without any overpeaking or oscillation problem has been achieved by utilizing the parasitic junction capacitances of dummy transistors as the compensation capacitance

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Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 1 )