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An 8-bit 200-MHz BiCMOS comparator

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2 Author(s)
P. J. Lim ; Center for Integrated Syst., Stanford Univ., CA, USA ; B. A. Wooley

The design of a fully differential BiCMOS comparator suitable for application in data conversion, instrumentation, and communication systems operating at video frequencies and above is discussed. By exploiting the advantages presented by the integration of both bipolar and CMOS devices within the same technology, the comparator dissipates less power than conventional bipolar designs without sacrificing operating speed. The comparator includes an input stage that combines MOS sampling with a bipolar regenerative amplifier. This stage dissipates no static power and, because the amplification is provided by a bipolar differential pair, no offset cancellation is needed to achieve 8-b precision. Furthermore, the need for preamplification and the attendant power-delay penalty associated with preamplifier overdrive recovery are avoided. An experimental version of the comparator, consisting of the BiCMOS regenerative input stage followed by a current-switched latch, has been integrated in a 0.8-μm BiCMOS technology with an area of 140×75 μm. This circuit performs comparisons to a precision of 8 b at rates up to 200 MHz. The entire circuit dissipates only 1.6 mW at the maximum clock rate while operating from a single 5-V supply

Published in:

IEEE Journal of Solid-State Circuits  (Volume:25 ,  Issue: 1 )