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An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption

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4 Author(s)
Hosotani, S. ; Mitsubishi Electr. Corp., Hyogo, Japan ; Miki, T. ; Maeda, A. ; Yazawa, N.

Low power consumption and small chip area (2.09 mm×2.15 mm) are achieved by introducing a new architecture to a subranging A/D converter. In this architecture, both coarse and fine A/D conversions can be accomplished. Consequently, a large number of comparators and processing circuits have been removed from the conventional subranging A/D converter. This architecture has been realized by the introduction of a chopper-type comparator with three input terminals which makes both coarse and fine comparisons by itself. The A/D converter has two 8-b sub/A/D converters which employ this new architecture, and they are pipelined to improve the conversion rate. Good experimental results have been obtained. Both the differential and the integral nonlinearity are less than ±0.5 LSB at a 20-megasample/s sample frequency. The effective resolution at 20-megasample/s sampling frequency is 7.4 b at a 1.97-MHz input frequency and 6.7 b at a 9.79-MHz input frequency. The A/D converter has been fabricated in a 1-μm CMOS technology

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 1 )

Date of Publication:

Feb 1990

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