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Offset reduction technique for use with high speed CMOS comparators

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2 Author(s)
Bruccoleri, M. ; SGS-Thomson Microelectron., Milan ; Cusinato, P.

The authors present a new input-referred offset reduction technique for use with a high speed regenerative latch. Thus allowing the use of this circuit as a comparator in sigma-delta converters and a gain reduction in the preamplifier stages which have to precede the latch in medium resolution (8 bit) and high resolution comparators (with offset cancellation)

Published in:

Electronics Letters  (Volume:32 ,  Issue: 13 )