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High-performance BiCMOS 100 K-gate array

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14 Author(s)
Gallia, J.D. ; Texas Instrum. Inc., Dallas, TX, USA ; Ah-Lyan Yee ; Chau, K.K. ; Wang, I.-F.
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A BiCMOS gate array in 0.8-μm technology with CMOS intrinsic gate delays of 100 ps plus 60 ps/fan-out and BiCMOS intrinsic delays of 200 ps with a 17-ps/fan-out drive factor is discussed. A compact base cell (750 μm2/gate) has been designed with full bipolar drive capability for the efficient layout of both primitive gates and large-arrayed macros, such as register files and multipliers. A 106 K-gate array has been built on a 1.14-cm2 chip with ECL I/O capability. The place and route in three levels of metal provide array utilization greater than 90%. The gate array was used to implement a 74 K-gate filter design with testability features such as JTAG and two-phase scan

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Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 1 )