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An on-chip smart memory for a data-flow CPU

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4 Author(s)
Uvieghara, G.A. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Nakagome, Y. ; Deog-Kyoon Jeong ; Hodges, D.

Register Alias Table (RAT) is a smart memory that is embedded in HPSm (High-Performance Substrate), a Berkeley data-flow CPU. It is a multiport memory that has content addressability and support for branch prediction and exception handling, in addition to conventional read and write operations. An experimental 1240-b smart memory chip is implemented in a 1.6-μm double-metal scalable CMOS process. This memory performs 15 operations within a cycle time of 100 ns, has 34658 transistors, occupies an area of 3.8 mm×5.2 mm, and dissipates 0.51 W

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 1 )