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Systolic random number generation for genetic algorithms

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2 Author(s)
Bland, I.M. ; Dept. of Comput. Sci., Reading Univ., UK ; Megson, G.M.

A parallel hardware random number generator for use with a VLSI genetic algorithm (GA) processing device is proposed. The design uses a systolic array of mixed congruential random number generators. The generators are constantly reseeded with the outputs of the proceeding generators to avoid significant biasing of the randomness of the array, which would result in longer times for the algorithm to converge to a solution

Published in:

Electronics Letters  (Volume:32 ,  Issue: 12 )