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An α-immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell

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3 Author(s)
Ishibashi, K. ; Hitachi Ltd., Tokyo, Japan ; Yamanaka, T. ; Shimohigashi, K.

The key technology for achieving the low-voltage operation is shown to be a polysilicon PMOS load (PPL) cell. The polysilicon PMOS device is successfully stacked on the bulk MOSFET, using 0.5-μm CMOS technology. The investigation emphasizes the soft error rate (SER) and the stability of the cell. The SER of the PPL cell at a supply voltage of 2 V is comparable to that of the conventional high-resistivity polysilicon load cell at a supply voltage of 5 V. The cell stability is also improved using a PPL cell, so that the low-voltage operation is assured

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Solid-State Circuits, IEEE Journal of  (Volume:25 ,  Issue: 1 )