Interface morphology and electrical properties of Pt/SrBi2Ta2O9(SBT)/CeO2/Si ferroelectric gate structure are characterized by considering the interactions among Bi, O, and Pt atoms during annealing process. It is found that the interfacial roughness of the Pt/SBT might be reduced during the annealing at 800 °C because the bottom side of the Pt electrode reacts with Bi atoms outdiffused from the SBT and the Bi–Pt alloys are molten at 765 °C, and the metallic Bi atoms are consumed by forming Bi oxide. Additionally, the capacitance and memory window of the ferroelectric gate structure annealed at 800 °C decrease to 69% and 80% of those values of the as-deposited gate structure, respectively, due to the additional capacitance and the voltage drop at the low dielectric Bi-oxide capacitor. In contrast, the leakage current characteristics are improved by two orders of magnitude after annealing at 800 °C for 30 min. © 1999 American Institute of Physics.